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Complexitylib.Models.RandomAccessMachine.Simulation.TMConfig.Sparse.Step.Internal.Layout

Sparse TM-step address and loading layout -- proof internals #

theorem Complexity.RAM.TMConfig.Sparse.addressOps_represents_internal {n : } {tm : TM n} {cfg : Complexity.Cfg n tm.Q} {store : Structured.Store} (hrepresents : Represents tm cfg store) (tape : Fin (n + 2)) :
theorem Complexity.RAM.TMConfig.Sparse.loadTapeOps_represents_internal {n : } {tm : TM n} {cfg : Complexity.Cfg n tm.Q} {store : Structured.Store} (hrepresents : Represents tm cfg store) (tape : Fin (n + 2)) :
theorem Complexity.RAM.TMConfig.Sparse.addressOps_address_internal {n : } {tm : TM n} {cfg : Complexity.Cfg n tm.Q} {store : Structured.Store} (hrepresents : Represents tm cfg store) (tape : Fin (n + 2)) (htapeCount : store (tapeCountReg n) = n + 2) :
Structured.Basic.execList (addressOps n tape) store (addressReg n) = cellReg n tape (tapeAt cfg tape).head
theorem Complexity.RAM.TMConfig.Sparse.loadTapeOps_symbol_internal {n : } {tm : TM n} {cfg : Complexity.Cfg n tm.Q} {store : Structured.Store} (hrepresents : Represents tm cfg store) (tape : Fin (n + 2)) (htapeCount : store (tapeCountReg n) = n + 2) :