Finite iteration of anti-checker selection rounds #
This module exposes exact base and successor equations for the dependent composition of prefix-length counter-selection circuits.
Zero selection rounds preserve the truth table and attach the empty labeled prefix.
The initial state-copy circuit has exactly one output gate per truth-table bit.
A nonempty prefix circuit evaluates the previous prefix circuit and then the counter-selection round indexed by that prefix length.
Serial composition gives exact additive size at every successor round.
Prepending a candidate to a target-labeled packed vector agrees exactly with the candidate-prefix encoding used by the counter circuit.
On a canonical target truth table, the round successor state is precisely the state obtained by consing the selected input.
The circuit-level counter estimate on a canonical state is the counter's semantic estimate of the target-labeled cons extension.
At every bounded prefix, the circuit-level round estimate is exactly the existing total estimator induced by the counter family.
Every bounded prefix circuit realizes a sequence of genuine greedy estimate-minimizing choices for the counter family's induced estimator.
The full state circuit realizes an estimate-selection trace of the exact length required by the anti-checker argument.
Projecting a canonical selection state to sample inputs recovers each selected input exactly.
The projected circuit evaluates by selecting the sample-input coordinates from the full iterated state.
Projecting away the labels and carried truth table costs exactly one output gate per required-round sample bit.
The projected circuit prints exactly the inputs of a full greedy estimate-selection trace.