Typed Boolean circuits #
This file defines the library's typed Boolean circuits. A Circuit B N M G is
a circuit over the basis B with N primary inputs, M output gates, and G
internal gates; its wiring makes it acyclic by construction. The file also
defines evaluation, depth, the size measure G + M, and complete bases.
Main definitions #
Gate— a gate over a basis, with a free negation flag on each inputCircuit— an acyclic Boolean circuit (well-formedness by construction)Circuit.wireValue,Circuit.eval— evaluation of wires and outputsCircuit.wireDepth— depth of a wire in the circuit DAGCircuit.outputDepth— depth of a single output gateCircuit.depth— depth of a (possibly multi-output) circuitCircuit.size— the number of internal and output gatesCompleteBasis— typeclass for functionally complete bases
Main results #
CompleteBasis.of_simulation— completeness transfers to any basis that can simulate the circuits of a complete basis
A gate in a circuit over basis B with W wires available as inputs.
The gate's fan-in must satisfy the arity constraint of its operation, and each
input is wired to one of the W available wires.
- op : B.Op
The basis operation this gate computes.
- fanIn : ℕ
The number of inputs this gate reads.
- arityOk : (B.arity self.op).satisfiedBy self.fanIn
The wire each of the gate's
fanIninputs is connected to.Per-input negation flag. Negations are free under this library's size convention.
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A Boolean circuit over basis B with N inputs, M outputs, and G
internal gates.
All gates reference wires from Fin (N + G). The acyclic field ensures
that internal gate i only reads wires 0, …, N + i − 1, preventing cycles.
The internal gates; gate
idrives wireN + i.The output gates; output bit
jis the value of gateoutputs j.Acyclicity: internal gate
ionly reads wires0, …, N + i − 1.
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Value of wire w when the circuit is fed input.
The first N wires carry the primary inputs. Wire N + i carries the
output of internal gate i.
Equations
- One or more equations did not get rendered due to their size.
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Depth of wire w in the circuit DAG.
Primary inputs have depth 0. Wire N + i (internal gate i) has depth
1 + max over input wires.
Equations
- One or more equations did not get rendered due to their size.
Instances For
The library's circuit size: internal gates plus output gates.
Primary input vertices are not counted, and the negation flags on gate inputs have zero cost. Some texts instead count input vertices and explicit NOT gates; those conventions agree only up to additive/linear overhead, not on exact size bounds.
Instances For
If every circuit over B₁ can be simulated by a circuit over B₂
(possibly with a different number of internal gates), then completeness
of B₁ implies completeness of B₂.
This is the generic tool for proving new bases complete: show you can compile each gate of a known-complete basis into a subcircuit of the new basis.