Streamable deterministic unrolling arithmetic #
This module exposes the base-independent gate count of one packed transition layer and closed forms for the configuration base, first unused wire, and gate count after any canonical deterministic trace prefix.
These are pure structural facts about the direct-unrolling circuit. They are
intended to be consumed by an append-only log-space serializer without making
that serializer reproduce the recursive TraceBuild arithmetic at run time.
Main results #
CircuitUnrolling.size_nextFormula_eq_directStepFormulaSize— formula size ignores absolute wire bases.CircuitUnrolling.stepFragmentSize_eq_directStepSize— every packed layer at a fixed horizon has one exact size.TM.directPrefixTraceBuild_configBase,TM.directPrefixTraceBuild_available, andTM.directPrefixTraceBuild_size— closed forms for deterministic prefixes.TM.directUnrollingRawCircuit_eq_init_append_steps— the complete direct raw circuit is initialization, a flat canonical layer list, and acceptance.
Absolute incoming configuration and choice-wire numbers do not affect a next-configuration formula's tree size.
At a fixed horizon, every packed transition fragment has the same exact gate count, independently of its incoming configuration and choice wires.
After i ≤ T deterministic transition layers, the first unused wire is
the primary prefix, initial configuration width, and i complete layer sizes.
After i ≤ T deterministic transition layers, the trace prefix contains
the initial configuration block followed by i equal-size packed layers.
The circuit accumulated after i ≤ T layers is the initialization fragment
followed by the first i canonical closed-form transition fragments.
The complete deterministic trace fragment is initialization followed by all canonical closed-form transition fragments in layer order.
The final deterministic configuration block begins after exactly T
base-independent transition fragments.
The positive direct-unrolling raw circuit is exactly the initialization fragment, the flattened canonical transition layers, and one final acceptance gate at the closed-form final configuration base.