Circuit layouts for bounded Turing-machine traces #
This file defines the wire layout used to unroll a bounded nondeterministic
Turing-machine trace. A configuration is represented by one-hot atoms for its
state, tape-head positions, and tape-cell symbols. Head positions range over
Fin (T + 1) and cells over Fin (T + 2); the extra cell keeps output cell
one present even at the zero-step horizon.
The primary-input layout is independent of the configuration layout. This
lets later clients place random choices, data, and auxiliary inputs wherever
they choose. prefixInputWires supplies the canonical choices-first order.
Equations
- One or more equations did not get rendered due to their size.
- Complexity.CircuitUnrolling.instDecidableEqTapeSlot.decEq Complexity.CircuitUnrolling.TapeSlot.input Complexity.CircuitUnrolling.TapeSlot.input = isTrue ⋯
- Complexity.CircuitUnrolling.instDecidableEqTapeSlot.decEq Complexity.CircuitUnrolling.TapeSlot.input (Complexity.CircuitUnrolling.TapeSlot.work i) = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqTapeSlot.decEq Complexity.CircuitUnrolling.TapeSlot.input Complexity.CircuitUnrolling.TapeSlot.output = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqTapeSlot.decEq (Complexity.CircuitUnrolling.TapeSlot.work i) Complexity.CircuitUnrolling.TapeSlot.input = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqTapeSlot.decEq (Complexity.CircuitUnrolling.TapeSlot.work i) Complexity.CircuitUnrolling.TapeSlot.output = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqTapeSlot.decEq Complexity.CircuitUnrolling.TapeSlot.output Complexity.CircuitUnrolling.TapeSlot.input = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqTapeSlot.decEq Complexity.CircuitUnrolling.TapeSlot.output (Complexity.CircuitUnrolling.TapeSlot.work i) = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqTapeSlot.decEq Complexity.CircuitUnrolling.TapeSlot.output Complexity.CircuitUnrolling.TapeSlot.output = isTrue ⋯
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A named tape on which a machine transition may write.
- work
{k : ℕ}
(i : Fin k)
: WritableSlot k
One of the machine's work tapes.
- output
{k : ℕ}
: WritableSlot k
The output tape.
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- One or more equations did not get rendered due to their size.
- Complexity.CircuitUnrolling.instDecidableEqWritableSlot.decEq (Complexity.CircuitUnrolling.WritableSlot.work i) Complexity.CircuitUnrolling.WritableSlot.output = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqWritableSlot.decEq Complexity.CircuitUnrolling.WritableSlot.output (Complexity.CircuitUnrolling.WritableSlot.work i) = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqWritableSlot.decEq Complexity.CircuitUnrolling.WritableSlot.output Complexity.CircuitUnrolling.WritableSlot.output = isTrue ⋯
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The zero-based position of a writable tape in work/output order.
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Regard a writable work/output slot as a general named tape slot.
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The zero-based position of a named tape in input/work/output order.
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Select a named tape from a machine configuration.
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The zero-based index of an alphabet symbol in zero/one/blank/start order.
Equations
- Complexity.CircuitUnrolling.symbolIndex Complexity.Γ.zero = ⟨0, Complexity.CircuitUnrolling.symbolIndex._proof_4⟩
- Complexity.CircuitUnrolling.symbolIndex Complexity.Γ.one = ⟨1, Complexity.CircuitUnrolling.symbolIndex._proof_6⟩
- Complexity.CircuitUnrolling.symbolIndex Complexity.Γ.blank = ⟨2, Complexity.CircuitUnrolling.symbolIndex._proof_8⟩
- Complexity.CircuitUnrolling.symbolIndex Complexity.Γ.start = ⟨3, Complexity.CircuitUnrolling.symbolIndex._proof_10⟩
Instances For
A one-hot proposition about a bounded machine configuration.
- state
{k : ℕ}
{tm : NTM k}
{T : ℕ}
(q : tm.Q)
: ConfigAtom tm T
The machine is in the indicated state.
- head
{k : ℕ}
{tm : NTM k}
{T : ℕ}
(tape : TapeSlot k)
(position : Fin (T + 1))
: ConfigAtom tm T
A named tape's head is at the indicated position.
- cell
{k : ℕ}
{tm : NTM k}
{T : ℕ}
(tape : TapeSlot k)
(position : Fin (T + 2))
(symbol : Γ)
: ConfigAtom tm T
A named tape's cell contains the indicated symbol.
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Equations
- One or more equations did not get rendered due to their size.
- Complexity.CircuitUnrolling.instDecidableEqConfigAtom.decEq (Complexity.CircuitUnrolling.ConfigAtom.state q) (Complexity.CircuitUnrolling.ConfigAtom.head tape position) = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqConfigAtom.decEq (Complexity.CircuitUnrolling.ConfigAtom.state q) (Complexity.CircuitUnrolling.ConfigAtom.cell tape position symbol) = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqConfigAtom.decEq (Complexity.CircuitUnrolling.ConfigAtom.head tape position) (Complexity.CircuitUnrolling.ConfigAtom.state q) = isFalse ⋯
- Complexity.CircuitUnrolling.instDecidableEqConfigAtom.decEq (Complexity.CircuitUnrolling.ConfigAtom.cell tape position symbol) (Complexity.CircuitUnrolling.ConfigAtom.state q) = isFalse ⋯
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State/head/cell sum representation used to construct the explicit layout.
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- One or more equations did not get rendered due to their size.
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Named tapes are explicitly equivalent to their input/work/output indices.
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Alphabet symbols are explicitly equivalent to their four layout indices.
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Tape-head atoms are explicitly equivalent to their contiguous layout indices.
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Explicit equivalence between configuration atoms and their block indices.
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- One or more equations did not get rendered due to their size.
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Finite enumeration of configuration atoms in explicit wire order.
Zero-based index of a machine state in the fixed finite-state ordering.
Equations
- Complexity.CircuitUnrolling.stateIndex tm q = ↑((Fintype.equivFin tm.Q) q)
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Zero-based index of an atom within one configuration block.
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- One or more equations did not get rendered due to their size.
- Complexity.CircuitUnrolling.configIndex tm T (Complexity.CircuitUnrolling.ConfigAtom.state q) = Complexity.CircuitUnrolling.stateIndex tm q
- Complexity.CircuitUnrolling.configIndex tm T (Complexity.CircuitUnrolling.ConfigAtom.head tape position) = Fintype.card tm.Q + ↑tape.index * (T + 1) + ↑position
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The explicit arithmetic index agrees with the atom-layout equivalence.
Every explicit atom index lies inside its configuration block.
State atoms occupy the first portion of a configuration block.
Head atoms follow states, ordered first by tape and then position.
Cell atoms follow heads, ordered by tape, position, and symbol.
Absolute wire carrying a configuration atom after a given prefix.
Equations
- Complexity.CircuitUnrolling.configWire tm T base atom = base + Complexity.CircuitUnrolling.configIndex tm T atom
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Boolean truth value of an atom in a concrete configuration.
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- One or more equations did not get rendered due to their size.
- Complexity.CircuitUnrolling.ConfigAtom.value c (Complexity.CircuitUnrolling.ConfigAtom.state q) = decide (c.state = q)
- Complexity.CircuitUnrolling.ConfigAtom.value c (Complexity.CircuitUnrolling.ConfigAtom.head tape position) = decide ((Complexity.CircuitUnrolling.TapeSlot.get c tape).head = ↑position)
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Locations of choice and input-data bits among an existing wire prefix.
Wire carrying each nondeterministic choice bit.
Wire carrying each input-data bit.
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Canonical input order: all choice bits, followed by all input-data bits.
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In the canonical layout, choice i is primary input wire i.
In the canonical layout, data bit i follows all T choice wires.
A Boolean source used by the one-gate initialization fragment.
- constant
{available : ℕ}
(value : Bool)
: InitSource available
A constant Boolean value.
- wire
{available : ℕ}
(input : Fin available)
(negated : Bool)
: InitSource available
An existing wire, optionally negated.
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Semantic value of an initialization source under a prefix assignment.
Equations
- Complexity.CircuitUnrolling.InitSource.value assignment (Complexity.CircuitUnrolling.InitSource.constant value) = value
- Complexity.CircuitUnrolling.InitSource.value assignment (Complexity.CircuitUnrolling.InitSource.wire input negated) = (negated ^^ assignment input)
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Compile an initialization source to exactly one raw gate.
Equations
- (Complexity.CircuitUnrolling.InitSource.constant value).gate = Complexity.CircuitCode.RawGate.constant 0 value
- (Complexity.CircuitUnrolling.InitSource.wire input negated).gate = Complexity.CircuitCode.RawGate.copy (↑input) negated
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Source for the initial one-hot value of a bounded configuration atom.
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- One or more equations did not get rendered due to their size.
- Complexity.CircuitUnrolling.initSource tm T n available layout (Complexity.CircuitUnrolling.ConfigAtom.state q) = Complexity.CircuitUnrolling.InitSource.constant (decide (tm.qstart = q))
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Configuration atoms listed in exactly their explicit wire order.
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One-gate-per-atom fragment producing the initial configuration block.
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- One or more equations did not get rendered due to their size.