Raw parity-circuit fragments #
The compiler in this module emits one false initializer and three shared gates per selected existing wire. It exposes exact size, topological well-formedness, and iterative evaluation theorems for use in larger raw-circuit builders.
Parity compilation emits exactly one initializer and three gates per selected wire.
The last gate emitted by parity compilation carries its result.
The parity fragment is topologically ordered whenever every selected reference names a pre-existing wire.
The parity fragment is a valid nonempty raw circuit whenever its selected references name pre-existing wires.
Iterative evaluation of the parity fragment returns the XOR of the selected input bits.
Fragment evaluation appends the parity value while preserving every pre-existing memo wire.