Variable-parameter depth reduction for parity circuits #
This module composes the variable-parameter layer iterator with the parity
top-gate obstruction. A circuit of logical depth at most rounds + 1 needs
only rounds restriction steps: the final unreduced AND or OR is handled as a
bounded-width normal form.
Under the explicit per-round switching and survivor inequalities, any parity
circuit forces retained rounds <= treeBound rounds. If the chosen schedule
ends above that tree bound, the circuit cannot compute parity. This is the
complete structural contradiction with the source-faithful d - 1 round
count; selecting closed-form parameters remains a separate arithmetic task.
A depth-rounds + 1 parity circuit satisfying an explicit reduction
schedule forces the final survivor count below the final tree bound, with no
restriction on the placement of NOT gates.
Compatibility wrapper for the checked input-negation presentation.
Parameterized rounds-step parity lower bound with one unreduced top
layer: a schedule ending above its final tree allowance rules out the circuit,
with arbitrary internal NOT gates.
Compatibility wrapper for the checked input-negation presentation.