The unbounded-fan-in AC0 basis #
This module models the source convention used by Hastad's small-depth lower
bound. AND and OR gates have arbitrary finite fan-in. NOT is explicit in the
generic circuit syntax, but the source-facing cost charges only AND/OR gates
and the source-facing logical depth gives NOT zero delay. The checked class
presentation requires every NOT to read an original input. A stronger
Circuit.NormalForm predicate additionally records alternation of adjacent
AND/OR gates.
Equations
- Algebraic.AC0.instDecidableEqOp.decEq Algebraic.AC0.Op.not Algebraic.AC0.Op.not = isTrue ⋯
- Algebraic.AC0.instDecidableEqOp.decEq Algebraic.AC0.Op.not (Algebraic.AC0.Op.and arity) = isFalse ⋯
- Algebraic.AC0.instDecidableEqOp.decEq Algebraic.AC0.Op.not (Algebraic.AC0.Op.or arity) = isFalse ⋯
- Algebraic.AC0.instDecidableEqOp.decEq (Algebraic.AC0.Op.and arity) Algebraic.AC0.Op.not = isFalse ⋯
- Algebraic.AC0.instDecidableEqOp.decEq (Algebraic.AC0.Op.and a) (Algebraic.AC0.Op.and b) = if h : a = b then h ▸ isTrue ⋯ else isFalse ⋯
- Algebraic.AC0.instDecidableEqOp.decEq (Algebraic.AC0.Op.and arity) (Algebraic.AC0.Op.or arity_1) = isFalse ⋯
- Algebraic.AC0.instDecidableEqOp.decEq (Algebraic.AC0.Op.or arity) Algebraic.AC0.Op.not = isFalse ⋯
- Algebraic.AC0.instDecidableEqOp.decEq (Algebraic.AC0.Op.or arity) (Algebraic.AC0.Op.and arity_1) = isFalse ⋯
- Algebraic.AC0.instDecidableEqOp.decEq (Algebraic.AC0.Op.or a) (Algebraic.AC0.Op.or b) = if h : a = b then h ▸ isTrue ⋯ else isFalse ⋯
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Arity of an AC0 operation.
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Signature of the arbitrary-fan-in Boolean basis.
Equations
- Algebraic.AC0.signature = { Op := Algebraic.AC0.Op, Arity := Algebraic.AC0.arity }
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Standard Boolean semantics. Empty conjunction is true and empty disjunction is false.
Equations
- Algebraic.AC0.interpretation Algebraic.AC0.Op.not input = !input 0
- Algebraic.AC0.interpretation (Algebraic.AC0.Op.and arity) input = decide (∀ (k : Fin (Algebraic.AC0.signature.Arity (Algebraic.AC0.Op.and arity))), input k = true)
- Algebraic.AC0.interpretation (Algebraic.AC0.Op.or arity) input = decide (∃ (k : Fin (Algebraic.AC0.signature.Arity (Algebraic.AC0.Op.or arity))), input k = true)
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Hastad's size convention: count AND and OR gates, not input negations.
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The two connectives whose adjacent levels are merged in normal form.
- and : Connective
- or : Connective
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Forget fan-in while retaining whether an operation is AND or OR.
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A NOT line is a source literal precisely when it reads an original input.
Equations
- Algebraic.AC0.Line.NegationAtInput { op := Algebraic.AC0.Op.not, wires := wires } = ∃ (input : Fin n), wires 0 = Cslib.Circuits.Wire.input input
- Algebraic.AC0.Line.NegationAtInput { op := Algebraic.AC0.Op.and arity, wires := wires } = True
- Algebraic.AC0.Line.NegationAtInput { op := Algebraic.AC0.Op.or arity, wires := wires } = True
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Every direct AND/OR predecessor has the opposite connective. NOT lines are treated as input literals and impose no connective condition.
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- One or more equations did not get rendered due to their size.
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Every NOT gate in a program reads an original input.
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No AND gate directly reads an AND gate and no OR gate directly reads an OR gate.
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- Algebraic.AC0.Program.Alternating Cslib.Circuits.Program.empty = True
- Algebraic.AC0.Program.Alternating (program.gate line) = (Algebraic.AC0.Program.Alternating program ∧ Algebraic.AC0.Line.AlternatesAfter program line)
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Arrival-time semantics for source gate levels. Input negations are literal annotations and therefore have zero delay; AND and OR add one level.
Equations
- Algebraic.AC0.logicalDepthInterpretation Algebraic.AC0.Op.not input = input 0
- Algebraic.AC0.logicalDepthInterpretation (Algebraic.AC0.Op.and n) input = (Fin.foldl n (fun (depth : ℕ) (argument : Fin n) => max depth (input argument)) 0).succ
- Algebraic.AC0.logicalDepthInterpretation (Algebraic.AC0.Op.or n) input = (Fin.foldl n (fun (depth : ℕ) (argument : Fin n) => max depth (input argument)) 0).succ
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Every NOT gate in the circuit is an input literal.
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Logical depth of each designated output in Hastad's convention.
Equations
- Algebraic.AC0.Circuit.logicalOutputDepths circuit = circuit.eval Algebraic.AC0.logicalDepthInterpretation fun (x : Fin n) => 0
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Maximum number of AND/OR levels on a designated input-output path.
Equations
- Algebraic.AC0.Circuit.logicalDepth circuit = Fin.foldl m (fun (depth : ℕ) (output : Fin m) => max depth (Algebraic.AC0.Circuit.logicalOutputDepths circuit output)) 0
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A one-output circuit's logical depth is the depth of its unique output.
Source-facing normal form: negations are input literals and consecutive AND/OR gates alternate.
Equations
- Algebraic.AC0.Circuit.NormalForm circuit = (Algebraic.AC0.Circuit.NegationsAtInputs circuit ∧ Algebraic.AC0.Program.Alternating circuit.program)
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Strong normal form in particular places every negation at an input.
Logical depth as a resource function of a nonuniform family.
Equations
- Algebraic.AC0.Family.logicalDepth family n = Algebraic.AC0.Circuit.logicalDepth (family.circuit n)
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Every member of the family is in the source-facing normal form.
Equations
- Algebraic.AC0.Family.NormalForm family = ∀ (n : ℕ), Algebraic.AC0.Circuit.NormalForm (family.circuit n)
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Every family member has only input-level negations.
Equations
- Algebraic.AC0.Family.NegationsAtInputs family = ∀ (n : ℕ), Algebraic.AC0.Circuit.NegationsAtInputs (family.circuit n)
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Strong family normal form implies the input-negation invariant used by the switching-lemma development.
One source-level depth bound works at every input width.
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An unrestricted small-depth family has polynomial AND/OR cost and constant logical depth. Internal NOT gates are allowed in this raw presentation.
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A checked AC0 family has polynomial AND/OR cost, constant logical depth,
and only input-level negations. Alternation is available separately through
Family.NormalForm but is not needed for the class definition.
Equations
- One or more equations did not get rendered due to their size.
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Forgetting the input-negation invariant yields a raw small-depth family.
Nonuniform AC0 computability of a one-output Boolean target family.
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- One or more equations did not get rendered due to their size.
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Raw nonuniform AC0 computability, allowing NOT gates at arbitrary internal
wires. Dual-rail normalization proves this presentation equivalent to
Computable.
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- One or more equations did not get rendered due to their size.