The iterated switching contradiction for parity circuits #
This module connects iterated semantic depth reduction to exact parity
resilience at a designated circuit output. If a one-output circuit computes
parity, any ShallowUpTo witness covering that output forces the restriction
to leave at most the common decision-tree allowance many variables live.
Combining that fact with exists_shallowUpTo_with_liveCount gives the central
parameterized contradiction: a survivor schedule satisfying the explicit
switching inequalities rules out the circuit whenever its final value exceeds
the tree-depth allowance. Closed-form parameter selection is intentionally a
separate arithmetic layer.
A shallow invariant covering a parity-computing wire forces the live count below the common tree-depth allowance.
Every designated output depth is at most the circuit's maximum logical output depth.
A circuit logical-depth bound covers each designated output wire in the underlying program.
Exact circuit computation of parity identifies the scalar function on its unique designated output wire.
A shallow invariant covering a parity circuit's output leaves at most the tree-depth allowance many variables live.
Any parity circuit satisfying the iterated switching premises forces the final survivor schedule below the common tree-depth allowance, with arbitrary internal NOT gates.
Compatibility wrapper for the checked input-negation presentation.
Parameterized iterated-switching lower bound: if the survivor schedule ends above the tree allowance, the circuit cannot compute parity, even with arbitrary internal NOT gates.
Compatibility wrapper for the checked input-negation presentation.