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Complexitylib.SAT.Tseitin.Machine.Internal.FrontEndSpec

Hoare specification for the Tseitin reduction front end #

reductionFrontEndTM first initializes the fresh-variable register to one more than the source bit length and then validates the source encoding. This module composes the two framed contracts. The sequence boundary is an exact no-op on the parked input, unary registers, and empty output accumulator.

The resulting postcondition records all state needed by the branch assembly:

Main results #

Work-register family established by seedFreshTM: the fresh register contains the source bit length plus one and the remaining five registers are zero.

Equations
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Instances For

    Every initialized front-end register is parked.

    The structural front-end budget is bounded by a convenient linear polynomial with one coefficient.

    Framed front-end execution. Starting from the ordinary initial tape layout, initialize all six registers and validate z. Validation preserves the initialized register family exactly and leaves its Boolean verdict at output cell one.

    Rounded linear-time form of the front-end contract, ready for later polynomial assembly.