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Complexitylib.Models.RandomAccessMachine.Simulation.RegisterStore.Machine.Instruction.Load

Indirect sparse-store load instructions -- proof internals #

theorem Complexity.RAM.RegisterStore.Machine.indirectLoadInstructionTM_hoareTime_frame_internal {n : ℕ} (tapes : BinaryInstructionTapes n) (store : Store) (destination addressRegister : ℕ) (emittedBits : List Bool) (initialWork : Fin n → Tape) (inp₀ out₀ : Tape) (hcanonical : Canonical store) (hinitial : EntryLookupStaticReady tapes.lhsLookup store initialWork) (hreplacement : (initialWork tapes.update.replacement).HasBinaryNat 0) (hinput : TM.Parked inp₀) (houtput : out₀.HasBinaryPrefix emittedBits) :
(indirectLoadInstructionTM tapes destination addressRegister).HoareTime (fun (inp : Tape) (work : Fin n → Tape) (out : Tape) => inp = inp₀ ∧ work = initialWork ∧ out = out₀) (fun (inp : Tape) (work : Fin n → Tape) (out : Tape) => inp = inp₀ ∧ IndirectLoadInstructionResult tapes store destination addressRegister initialWork work ∧ out.HasBinaryPrefix (emittedBits ++ List.flatMap Entry.encode (write store destination (read store (read store addressRegister))))) (indirectLoadInstructionTime tapes store destination addressRegister)

Exact semantic and time contract for one indirect sparse-register load.