RAM sparse-entry decoder — definitions #
One sparse register entry contains two consecutive self-delimiting words: its
address and value. entryDecodeTM gives each word its own target, counter, and
width tapes so the two checked word decoders compose without a clearing phase.
Seven pairwise-distinct work tapes used by one sparse-entry decoder.
Tape assignment in the order source, address, value, address counter, address width, value counter, value width.
- injective : Function.Injective self.idx
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Encoded entry-stream source tape.
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Decoded address target tape.
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Decoded value target tape.
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Binary loop counter used while decoding the address.
Equations
- tapes.addressCounter = tapes.idx 3
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Preserved address payload-width tape.
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- tapes.addressWidth = tapes.idx 4
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Binary loop counter used while decoding the value.
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- tapes.valueCounter = tapes.idx 5
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Preserved value payload-width tape.
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- tapes.valueWidth = tapes.idx 6
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Source, address target, and address marker are pairwise distinct.
Source, value target, and value marker are pairwise distinct.
Decode the address word and then the value word of one sparse entry.
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Exact runtime for decoding both words, including the composition seam.
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Decode both entry words with unary markers. The former counter tapes serve
as address and value markers; the two width tapes are left untouched so this
machine can replace entryDecodeTM inside the established seven-tape ABI.
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Exact runtime of the optimized two-word decoder, including its composition seam.
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