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Complexitylib.Classes.PPoly.Uniform.Preprocessing.Defs

Inputs for uniform circuit-family evaluation #

The verified serialized evaluator consumes a pair of a tagged circuit code and the circuit input. A uniformity generator consumes unary length instead. This module names the pure preprocessing map connecting those interfaces.

On input x, run the prospective uniformity generator on 1^|x| and pair the resulting circuit code with the unchanged input.

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