Serialized circuit-evaluator machine #
This module exposes the audited front end for a deterministic evaluator of serialized circuit families. It validates the outer self-delimiting pair, stages its code and input components on separate appendable work tapes, and exposes the verified quadratic-time memoized evaluator from raw input through its final verdict.
Main results #
pair_mem_circuitEvalLanguage_iffidentifies the target language on canonical paired inputs.pairStageTM_hoareTimegives the total staged-input contract in linear time.Machine.evalFamilyCoreTM_hoareTimegives the total staged-core contract in concrete quadratic time.Machine.evalFamilyTM_decidesInTimeproves the complete evaluator decidescircuitEvalLanguage, andMachine.evalFamilyTime_bigO_quadraticgives its polynomial bound.Machine.emitNatCodeTM_hoareTimeSpaceemits terminated-unary natural codes from binary work tapes with reusable scratch and an all-prefix space bound.Machine.emitRawGateTM_hoareTimeSpaceemits complete raw-gate codes from two preserved binary wire references.Machine.emitRawGateStepTM_hoareTimeSpaceadditionally advances the first-unused-wire counter after one emitted gate.
Membership in the evaluator language is successful Boolean evaluation.
A canonical outer pair belongs to the evaluator language exactly when its tagged circuit code evaluates to true on the paired input.
Pairing a family's canonical member code with an input recognizes exactly the language decided by that family.
Every staged endpoint leaves the output at cell one with the canonical left-marker invariant, ready for the evaluator core to overwrite its verdict.
The pair-staging machine validates every outer input and, in linear time, either rejects it without dirtying work tapes or exposes appendable code and input prefixes for the evaluator core.