Sequential fixed-width evaluator wire layout -- definitions #
The evaluator receives a description code followed by one sample input. It then compiles one formula fragment per bounded gate slot. This module assigns absolute wires to primary inputs and earlier gate results without yet building or executing the concatenated raw circuit.
The numeric prefix schedule depends only on the public exact gate-formula size, so later compilation and streaming constructions share one wire layout.
Number of incoming wires: description code followed by one sample input.
Equations
- Complexity.CircuitCode.FixedWidth.Description.EvaluationLayout.baseWireCount inputWidth gateBound = Complexity.CircuitCode.FixedWidth.codeWidth inputWidth gateBound + inputWidth
Instances For
Gate-formula size at a natural slot index, with zero outside the bound.
Equations
- One or more equations did not get rendered due to their size.
Instances For
Total gate-formula size of the first count slots.
Equations
- One or more equations did not get rendered due to their size.
- Complexity.CircuitCode.FixedWidth.Description.EvaluationLayout.prefixSize inputWidth gateBound 0 = 0
Instances For
Number of wires available before compiling one gate-slot formula.
Equations
- One or more equations did not get rendered due to their size.
Instances For
Absolute output wire assigned to one compiled gate-slot formula.
Equations
- One or more equations did not get rendered due to their size.
Instances For
Lift a prior local gate index to the global bounded slot type.
Equations
- Complexity.CircuitCode.FixedWidth.Description.EvaluationLayout.earlierSlot slot earlier = ⟨↑earlier, ⋯⟩
Instances For
One-node formulas naming the primary inputs and earlier gate results available to a particular gate slot.
Equations
- One or more equations did not get rendered due to their size.
Instances For
Formula computing one sequentially laid-out encoded gate slot.
Equations
- One or more equations did not get rendered due to their size.