One complete constructive greedy-scheduler stage #
This module builds the fixed-wire preprocessing omitted by the
rank-list-level selector. A stage input contains a power-of-two array of
previously occupied points followed by the current target. An explicit
coordinatewise GF(2^width) addition circuit forms point - target (the same
as point + target in characteristic two), and the verified guarded-rank,
sort, least-missing, and unrank pipeline selects a disjoint recovery-line
direction.
Coordinatewise packed vector addition #
Reorder one coordinate pair into the pair-of-whole-vectors layout.
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Exact gate count of one vector-addition coordinate circuit.
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- Algebraic.MassProduction.SchedulerStage.vectorAdditionCoordinateGateCount width = ∑ output : Fin width, Algebraic.MassProduction.additionCoordinateGateCount output
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Add two packed extension-field vectors coordinatewise.
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A pair of whole packed vectors, with the left vector first.
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Packed vector addition agrees exactly with field-vector addition.
Fixed input layout for the occupied points and target #
One bit of the point block in a (points..., target) stage input.
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- Algebraic.MassProduction.SchedulerStage.stagePointInputIndex depth vectorWidth record bit = Algebraic.MassProduction.blockPrefixIndex (finProdFinEquiv (record, bit))
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One bit of the final target block in a (points..., target) stage
input.
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- Algebraic.MassProduction.SchedulerStage.stageTargetInputIndex depth vectorWidth bit = Algebraic.MassProduction.blockSuffixIndex bit
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Inputs for one vector subtraction/addition inside the global stage layout.
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Raw parallel circuit before spelling its output count as
networkBits.
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Compute all point-minus-target vectors in parallel.
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- Algebraic.MassProduction.SchedulerStage.pointTargetDifferenceArrayCircuit dimension width depth = Algebraic.MassProduction.SchedulerStage.pointTargetDifferenceArrayRawCircuit dimension width depth
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Reading one generated difference block evaluates the corresponding vector-addition circuit on that point and the shared target.
Row-major packed bits of the occupied-point array.
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Canonical (points..., target) input expected by a scheduler stage.
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With correctly encoded point and target blocks, the preprocessing circuit
emits the packed characteristic-two difference point - target.
Point-array positions that differ from the current target. Positions equal to the target are valid padding and forbid no projective direction.
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- Algebraic.MassProduction.SchedulerStage.pointDifferentIndices points target = {record : Fin (Algebraic.MassProduction.Sorting.networkRecords depth) | points record ≠ target}
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For the canonical stage input, nonzero generated differences occur exactly at the non-padding point positions.
The complete stage and its geometric correctness #
Complete fixed-wire circuit for one greedy scheduling stage.
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A scheduler stage has exactly the gates of its difference array followed by the fresh-direction search.
Uniform polynomial ledger for one fully expanded scheduler stage.
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One fully explicit stage selects a canonical direction whose punctured line avoids every point represented in the input array.
The total-array capacity condition is a convenient sufficient form of one-stage correctness.
Public sentinel-aware vector-level form of one constructive stage.
Public vector-level form under total-array capacity.
The finite set of points appearing in a packed stage array. Its decidable equality is kept local to this definition.
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In particular, a sentinel-aware stage avoids the entire supplied point array.
A stage avoids the entire supplied power-of-two point array under total array capacity.