Khrapchenko's bound for circuits with shared gates and XOR/EQUIV gates #
This file extends the bounds of
Complexitylib.Algebraic.LowerBound.KarchmerWigderson.Sharing.Circuit from De Morgan circuits to
circuits over Extended.signature, the De Morgan basis together with binary XOR and EQUIV gates.
In SharedProgram.sq_card_edges_le, the Khrapchenko upper bound (k + 1) · X · |A| · |B| depends
on X = P.inputLeaves n, which counts only literal leaves on the original circuit inputs
0, …, n - 1 and ignores literal leaves reading shared variables z ≥ n. Consequently, a
binary gadget built solely from shared variables z₁, z₂ ≥ n—the four-leaf De Morgan expansion
Formula.xorGadget z₁ z₂ of z₁ ⊕ z₂ or Formula.equivGadget z₁ z₂ of z₁ ↔ z₂—has
inputLeaves n = 0. Allocating two shared values for the two input wires of each XOR/EQUIV gate
and substituting the gadget for the gate wire replaces every XOR/EQUIV gate by a zero-input-leaf
subformula while increasing the number of shared values by two, regardless of the gate's fan-out.
Hence a single-output circuit with c_DM AND and OR gates (Extended.deMorganCost), r XOR and
EQUIV gates (Extended.xorCost), and k gates of fan-out at least two (sharedGateCount) yields
a SharedProgram n K with K ≤ k + 2r and P.inputLeaves n ≤ c_DM + k + 2r + 1
(Extended.exists_sharedProgram_of_circuit). Thus:
|edges A B|² ≤ (k + 2r + 1) · (c_DM + k + 2r + 1) · |A| · |B|(Extended.sq_card_edges_le_cost),n² ≤ (k + 2r + 1) · (c_DM + k + 2r + 1)for parity (Extended.parity_sq_le_cost),(n + 1 - t) · t ≤ (k + 2r + 1) · (c_DM + k + 2r + 1)forthreshold t(Extended.threshold_mul_le_cost),(n - ⌊n/2⌋) · (⌊n/2⌋ + 1) ≤ (k + 2r + 1) · (c_DM + k + 2r + 1)for majority (Extended.majority_mul_le_cost), and both parity and majority require a superlinear numberc_DM = ω(n)of AND and OR gates wheneverk(n) = o(n)andr(n) = o(n)(Extended.isLittleO_cost_of_parity,Extended.isLittleO_cost_of_majority).
The theorems here carry the names of their De Morgan counterparts in the KW namespace, under
KW.Extended; with r = 0 their hypotheses specialize to those of the De Morgan versions. The
one difference is majority: Extended.mul_le_cost_of_majority takes 2m + 1 inputs, like
KW.mul_le_cost_of_majority, while
Extended.mul_le_cost_of_majority_of_four_mul_le and Extended.isLittleO_cost_of_majority
cover every input length n, at the price of the factor 4 in the hypothesis
4 · (k + 2r + 1) · (C + 1) ≤ n. (KW.isLittleO_cost_of_majority is stated for the odd
lengths 2m + 1 only.)
Khrapchenko, parity, threshold, and majority lower bounds #
Khrapchenko bound for circuits with k shared gates and r XOR/EQUIV gates. If an
extended-basis circuit computes f, at most k of its gates have fan-out at least two, and at
most r of its gates are XOR or EQUIV gates, then f satisfies Khrapchenko's bound with measure
(k + 2r + 1) · (c_DM + k + 2r + 1), where c_DM counts the AND and OR gates.
Rectangle edge bound for circuits with k shared gates and r XOR/EQUIV gates. If an
extended-basis circuit is 1 on A and 0 on B, then
|edges A B|² ≤ (k + 2r + 1) · (c_DM + k + 2r + 1) · |A| · |B|.
Parity in circuits with k shared gates and r XOR/EQUIV gates. An extended-basis
circuit computing the parity of n ≥ 1 bits satisfies
n² ≤ (k + 2r + 1) · (c_DM + k + 2r + 1).
Superlinear De Morgan cost for parity with few shared gates and few XOR/EQUIV gates. If
(k + 2r + 1) · (C + 1) ≤ n, every extended-basis circuit computing the parity of n bits with at
most k gates of fan-out at least two and at most r XOR/EQUIV gates has at least C · n AND
and OR gates.
Parity needs superlinear De Morgan gates when k(n) = o(n) and r(n) = o(n). If, for
every n, c n is an extended-basis circuit computing the parity of n bits with at most
k n = o(n) gates of fan-out at least two and at most r n = o(n) XOR/EQUIV gates, then the
number of AND and OR gates of c n grows faster than n.
Threshold functions in circuits with k shared gates and r XOR/EQUIV gates. For
1 ≤ t ≤ n, every extended-basis circuit computing threshold t satisfies
(n + 1 - t) · t ≤ (k + 2r + 1) · (c_DM + k + 2r + 1).
Majority in circuits with k shared gates and r XOR/EQUIV gates. Every extended-basis
circuit computing strict majority of n ≥ 1 bits satisfies
(n - ⌊n/2⌋) · (⌊n/2⌋ + 1) ≤ (k + 2r + 1) · (c_DM + k + 2r + 1).
Odd-input majority in circuits with k shared gates and r XOR/EQUIV gates. For odd n,
every extended-basis circuit computing strict majority of n bits satisfies
(⌊n/2⌋ + 1)² ≤ (k + 2r + 1) · (c_DM + k + 2r + 1).
Superlinear De Morgan cost for odd-input majority with few shared and XOR/EQUIV gates. If
(k + 2r + 1) · (C + 1) ≤ m, every extended-basis circuit computing the majority of 2m + 1 bits
with at most k gates of fan-out at least two and at most r XOR/EQUIV gates has at least C · m
AND and OR gates. With r = 0 this is the hypothesis of KW.mul_le_cost_of_majority; for every
input length see mul_le_cost_of_majority_of_four_mul_le.
Superlinear De Morgan cost for majority of any length with few shared and XOR/EQUIV
gates. The variant of mul_le_cost_of_majority for every input length n: if
4 · (k + 2r + 1) · (C + 1) ≤ n, every extended-basis circuit computing the majority of n bits
with at most k gates of fan-out at least two and at most r XOR/EQUIV gates has at least C · n
AND and OR gates.
Majority needs superlinear De Morgan gates when k(n) = o(n) and r(n) = o(n). If, for
every input length n, c n is an extended-basis circuit computing the majority of n bits with
at most k n = o(n) gates of fan-out at least two and at most r n = o(n) XOR/EQUIV gates, then
the number of AND and OR gates of c n grows faster than n. Unlike
KW.isLittleO_cost_of_majority, which indexes the family by m with 2m + 1 inputs, the family
here ranges over all input lengths.