Whole-basis lower bounds from aggregate capacity #
The same fixed polynomial-time family requires almost n bits of exact aggregate
capacity, with no bound on the number of special gates. Binary gates cost one bit;
special gates cost log₂ |M|, without rounding or guessed-output bits. If every
special register has at most r ≥ 2 states, the gate coefficient is 1 / log₂ r.
In particular two-state aggregate gates preserve a coefficient of one at arbitrary
depth and fan-in, with repeated slots and arbitrary special-to-special connections.
The circuit-to-summary argument belongs to the classical communication-complexity approach of Roychowdhury--Orlitsky--Siu (1994). The explicit family is the existing Chattopadhyay--Liao construction, with its full input length and balanced padding.
The fixed explicit family requires nearly one bit of exact aggregate capacity per input, with no sparsity condition on the special gates.
The rounded per-register capacity also has leading coefficient one.
A uniform bound on state cardinalities gives a whole-basis gate lower bound,
with the unrounded coefficient 1 / log₂ states.
Arbitrarily many two-state aggregate gates, together with all binary Boolean
gates, still require more than (1 - ε)n gates.