Boolean, modular, threshold, and symmetric aggregate gates #
AND and OR use multiplication in the two-element ring as a commutative monoid.
Their zero updates are noninvertible. Modular gates instead use its additive
monoid (written multiplicatively through Multiplicative), with an arbitrary
Boolean predicate on the residue. Slot-dependent contributions allow weighted
modular sums. Saturating addition computes nonnegative weighted thresholds,
and an arity-capped counter computes every predicate of the Hamming weight.
Each operation has unrestricted finite fan-in.
A two-state noncancellative aggregate computing conjunction.
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A two-state noncancellative aggregate computing disjunction.
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Any residue predicate on a slot-weighted modular sum is an aggregate gate.
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- One or more equations did not get rendered due to their size.
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Modular gate evaluation is precisely the weighted modular sum.
AND uses two aggregate states regardless of its fan-in.
OR uses two aggregate states regardless of its fan-in.
Capped counters enumerate exactly the integers from zero through the cap.
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- Algebraic.Aggregate.Capped.equivFin cap = { toFun := Algebraic.Aggregate.Capped.toFin, invFun := Algebraic.Aggregate.Capped.mk, left_inv := ⋯, right_inv := ⋯ }
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- Algebraic.Aggregate.Capped.instFintype cap = Fintype.ofEquiv (Fin (cap + 1)) (Algebraic.Aggregate.Capped.equivFin cap).symm
Capped addition, written multiplicatively for the aggregate interface.
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- One or more equations did not get rendered due to their size.
The register has exactly cap + 1 states.
Threshold register size depends on the threshold, not the fan-in or weights.
An arbitrary symmetric predicate uses exactly arity + 1 aggregate states.